1. Field of the Invention
The present invention relates to an image-processing circuit, and more particularly, to an image-processing circuit capable of reducing power consumption
2. Description of the Prior Art
Reference is made to FIG. 1 for a diagram of a prior art over-drive system 100. The over-drive system 100 can receive original frame data (such as frame (n−1), frame n and frame (n+1) depicted in FIG. 1), perform over-drive on the received frame data, and send the processed frame data to a liquid crystal display (LCD) device for displaying images. Over-drive technique is preferred due to its ability of accelerating the reaction rate and thus enhancing display quality of the LCD device. The over-drive system 100 includes an over-drive circuit 110 and a dynamic random access memory (DRAM) 120. The DRAM 120 is used for storing frame data, such as frame (n−1), frame n and frame (n+1) depicted in FIG. 1. By comparing the frame data stored in the DRAM 120 with that received by the over-drive system 100, the over-drive circuit 110 generates an over-drive frame accordingly. For example, upon receiving frame (n−1), the over-drive circuit 110 stores frame (n−1) into the DRAM 120; upon receiving frame n, the over-drive circuit 110 stores frame n into the DRAM 120, accesses frame (n−1) from the DRAM 120, and then compares frame (n−1) with frame n; upon receiving frame (n+1), the over-drive circuit 110 stores frame (n+1) into the DRAM 120, accesses frame n from the DRAM 120, and then compares frame n with frame (n+1). If frame (n+1) and frame n are identical, frame n is outputted directly for image display; if frame (n+1) differs from frame n, an over-drive frame, which is generated based on an over-drive table stored in the over-driver circuit 110, is then outputted for image display.
Therefore, each time the over-drive system 100 receives a frame, data needs be stored into the DRAM 120. The prior art system has high power consumption and can cause inconveniences for users.